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(a) Refer to Fig. 4–25 for a PLL frequency synthesizer. Design a synthesizer that will cover a range of 144 to 148 MHz in 5-kHz steps, starting at 144.000 MHz. Assume that the frequency standard operates at 5 MHz, that the M divider is fixed at some value, and that the N divider is programmable so that the synthesizer will cover the desired range. Sketch a diagram of your design, indicating the frequencies present at various points of the diagram.
(b) Modify your design so that the output signal can be frequency modulated with an audiofrequency input such that the peak deviation of the RF output is 5 kHz.
Fig. 4–25

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